Seminar 21.01.2013

Ultra Low Dielectric Constant Materials for Nanoelectronics

Mikhail R. Baklanov (IMEC, Leuven, Belgium)


Since the 1960's, the density of transistors in IC chip has been doubling every 1.5 years. The semiconductor industry primarily focused on improvements related to the speed of individual transistors and enhanced performance through scaling - by squeezing more transistors into a single IC device. By the early 1990s, the distances between IC components became incredibly small, and the relative effect of the interconnect delay became a greater portion of the overall signal propagation delay. The total resistance (R) of the interconnect structure and the capacitance (C) between the wires became a significant factor affecting chip performance by increasing RC delay of ICs. Replacement of traditional Al by low resistivity Cu decreases RC delay. However it was an enormous obstacle for semiconductor industry, since Al is deposited over the entire wafers surface and then patterned by reactive ion etching (RIE). Cu cannot be patterned by RIE because of too low vapor pressure of the reaction products, and new process had to be developed. As a result, the damascene process has been emerged as the industry standard. The dielectric layer is deposited and patterned first before the metal deposition. Then copper should fill a patterned dielectric by superfilling.

Different types of low-k materials have been considered. Relatively fast developed organosilicate (OSG) based low-k materials met significant challenges during their integration because of their porous structure. Low-k dielectrics based on organic polymers have low polarisability and therefore they are able to provide the lowest k-value without requiring the introduction of porosity. However, the efforts to integrate the organic materials into IC circuits have not been successful. In addition to poor mechanical and thermal properties the most important problems were related to relatively high coefficient of thermal expansion (CTE) in comparison with other IC components.

However, the efforts of scientists and engineers during the last 15 years made Cu/low-k technology mature. OSG low-k materials with k > 2.5 are already in the stage of integration into IC devices. According to ITRS Roadmap, there are known low-k candidates and solutions up to 14 nm technology nodes (2018). Advantage of OSG materials is similarity of their chemical properties to traditional SiO2 that makes possible to use traditional technological equipment and chemistries during the integration. Plasma Enhanced Chemical vapor Deposition (PECVD) has been the most important low-k deposition method for low-k materials with dielectric constant > 2.3.

This presentation will give an overview of low-k materials developed during the last 15 years, various challenges appearing during the integration, and also present approaches, problems and new tendencies related to ultra low-k materials for sub 14 nm technology nodes. The author is planning to discuss the most important existing interconnect challenges that can be considered as a subject of joint research.